(a) Field of the Invention
The invention relates to a programmable memory and its access method and, more particularly, to a programmable memory and its access method that perform multi-time programmable (MTP) recordings by N rows of one-time programmable (OTP) memory cells.
(b) Description of the Related Art
In the manufactures of a wafer, a super-twist nematic LCD (STN-LCD), or a thin-film transistor LCD (TFT-LCD), the finished products may have their respective electrical or optical characteristics. In order to improve the yield of manufacture, a typical method is to measure the actual characteristic parameters that are to be compared with target ones and then corrected by adjust procedures, where the adjust procedures are required to be easily implemented and permanently maintained. For example, the corrected values may be recorded by fuse burnout or by a non-volatile memory. The fuse may be burnt out by lasers or by applying high voltage/large current. Further, the non-volatile memory may be a one-time programmable memory (OTP memory) or a multi-time programmable memory (MTP memory), which are distinguished from each other according to their distinct architectures. Also, according to the difficulty of implement, the adjust procedures may be directly performed on the finished products or on memory cells to be affixed on the finished products.
It is clearly seen that the more flexibility is provided during manufacture if the adjust means, the fuse or the non-volatile memory, can be repeatedly set for several times. Thereby, a new corrected value can be set up once the specification is changed. However, compared with a one-time programmable memory cell such as a fuse, a multi-time programmable memory such as an EPROM, an EEPROM, or a flash memory requires additional circuits or complex fabrication processes to result in a high fabrication cost. Moreover, the yield of the multi-time programmable memory is closely related to semiconductor processes manipulated in a semiconductor factory, and thus the capacity risk is increased.
Hence, if multi-time programmable recordings are achieved by one-time programmable memory cells, the manufacture process is simplified and the fabrication cost is reduced under the circumstance that the flexibility of multi-time settings is maintained.
FIG. 1 shows a block diagram illustrating a programmable memory architecture described in U.S. Pat. No. 6,728,137. Referring to FIG. 1, multiple sets of one-time programmable memory blocks 15 are used in a programmable memory 10 to achieve multi-time programmable recordings. The programmable memory 10 writes-in and reads out data through row decoders 12 and column decoders 13 controlled by a control circuit 11. However, the programmable memory 10 requires additional record elements 14 to record which programmable memory block has been programmed.
FIG. 2 shows a block diagram illustrating another programmable memory architecture described in U.S. Publication No. 20050232039. Referring to FIG. 2, a multi-time programmable memory 20, similar to the programmable memory 10 shown in FIG. 1, includes multiple sets of adjusting one-time programmable (OTP) memory blocks 22 to achieve multi-time programmable recordings. When new data are stored in one OTP memory block 22, a write device 21 of the programmable memory 20 may simultaneously set an OTP element 24, which is used for selection purpose, corresponding to the OTP memory block 22. That is, the record element 14 shown in FIG. 1 is replaced by the OTP element 24. Further, multiple selection devices 23 of the programmable memory 20 are used to output latest updated data.
FIG. 3 shows a block diagram illustrating another programmable memory architecture described in U.S. Publication No. 20050253624. Referring to FIG. 3, a multi-time programmable memory 30 is similar to the multi-time programmable memory 20 shown in FIG. 2, where multiple sets of adjusting one-time programmable (OTP) memory blocks 22 are used to achieve multi-time programmable recordings. However, the OTP element 24 shown in FIG. 2 is replaced by multiple judge devices 34, as shown in FIG. 3. Hence, additional recordings about OTP element 24 are no longer needed.
Usually, since the destructive fuse structure functioning as the OTP cell is typically burnt out by lasers or by applying high voltage/large current, large areas must be reserved for spreading the fuse structure to avoid influencing surrounding circuits. On the other hand, if a typical charge capacitor type OTP memory is used, its stored data may be lost under adverse circumstances such as high temperature, fierce electromagnetic field or high intensity illumination, and thus the set corrected values are no longer permanently preserved. Under the circumstance, specific treatments on circuit design are needed, such as increase of voltage-regulated capacitors, voltage-limiting/current-limiting for power source, or formation of metallic shield layers used in IC layout. However, such remedies may result in a larger area of each OTP memory bit for several times when compared with each conventional MTP memory bit. Besides, the larger the number of bits to be programmed, the higher the opportunity of the occurrence of programmed failures becomes. For example, if the intensity of applied voltage/current is insufficient, the destructive fuse structure will not be burnt out. Moreover, if the intensity of applied voltage/current is great, the fierce stress due to repeated burn out operations may cause damages to an IC chip.
When we compare the three memory architecture described above, it is found they have similarities in their write-in procedures. Specifically, no matter how large the amount of the bit data are to be changed, a new set of OTP memory cells is always provided for storing the changed bit data. For example, even only one bit is to be changed, a new set of OTP memory cells must be provided. Further, in the above three memory architectures, each memory cell set has identical number of memory cells, and the output data contain bit data of only one memory cell set.